1. Field of the Invention
The invention relates in general to an isolation structure and a formation method thereof, and more particularly to an isolation structure with trenches for insulation and a formation method thereof.
2. Description of the Related Art
Generally speaking, with the increasing integration of a memory device, intervals between memory cells in the memory device are getting smaller and smaller. Thus, the isolation between the memory cells becomes one of key factors of the memory device performance. At present, the conventional local oxidation of silicon (LOCOS) has been gradually replaced with the shallow trench isolation (STI) technology because it has the drawback of forming a bird's beak. The STI technology is mainly to etch the silicon substrate to form trenches and then fill the material, such as silicon dioxide, between the memory cells to form the isolation region.
However, as shown in FIG. 1A, in a typical STI process, a pad oxide layer 420 and a nitride layer 430 are sequentially formed on a substrate 410, and then an opening 411 is formed in the pad oxide layer 420 and the nitride layer 430. After that, a trench 413 is formed via the opening 411 to expose a part of the substrate 410. A liner oxide layer (not shown) is then formed on the exposed part of the substrate 410. Afterward, an oxide material layer 450 (in FIG. 1B) is filled in the trench 413, chemical mechanical planarization (CMP) is performed for planarization, and the pad oxide layer 420 and the nitride layer 430 are removed. Then, a thermal oxide layer 460 and a conductive layer 480 are sequentially deposited to form a structure shown in FIG. 1B. As the amount of the oxide formed at the approximately right-angle corner is always less than that formed at other parts, the thermal oxide layer 460 formed around the top corners C1 become thinner (hereinafter “top corner thinning”). Besides, divot structures 481 formed after several wet clean/strip processes also cause the top corner thinning. Therefore, the memory device formed thereafter has a reduced breakdown voltage and an increased current leakage, so that the reliability of the memory device is degraded.
Furthermore, the increase of the aspect ratio of the trench may raise the fill-in issue due to the shrink of the dimension of the memory device to accordingly reduce the pitch of the memory device and the width of the trench. As shown in FIG. 1C, spacers 440 are formed on the sidewalls of the pad oxide layer 420 and the nitride layer 430 before etching the trench 413′, so that the top corner thinning might be avoided and the dimension of the top corners C2 can be pre-designed. However, as a result of forming the spacers 440, the aspect ratio of the trench 413′ becomes D/W, which apparently increases under the presupposition of the same depth D with respect to the trench 413 in FIG. 1A. Thus, as shown in FIG. 1D, when the oxide material layer 450 is filled in the trench 413′ through the reduced width W of the opening of the trench 413′, the fill-in issue may occur. That is, the oxide material layer 450 tends to block at the opening of the trench 413′, so that a void 470 may be formed easily.